This invention relates generally to a semiconductor integrated circuit device, and more particularly to a technique which will be useful when applied to a semiconductor integrated circuit device formed by a master slide approach such as a gate array.
The gate array is described, for example, in "Nikkei Microdevices", published by Nikkei McGraw-Hill Co., September issue, 1986, pp. 65-80. This reference explains CMOS (Complementary MOS) gate arrays having higher functions.
The gate array approach can form various many logic functions and memory functions by changing a wiring pattern to be applied to a master wafer. This change of the wiring pattern or the change of a circuit specification is decided in accordance with user's requirements.
An oscillation circuit used as a reference clock generation circuit of a microcomputer interface portion, for example, consists of basic cells for two adjacent input/output buffer circuits (I/O cells) and a crystal oscillator connected to each of bonding pads (hereinafter referred to as the "pad or pads") corresponding to the I/O cells.
A typical structure of this oscillation circuit is shown in FIG. 5 of the accompanying drawings. In this case, an inverter circuit 25 for oscillation as an amplification circuit portion of the oscillation circuit is composed of transistors having the same structure as those of an internal cell array region, that is, the transistors of an input circuit device region 26 for which any measures for electrostatic discharge damage are not made on the ground that a sufficient amplification effect can be obtained even though the transistors are small in size.
Recently, the amplification circuit described above is composed of a CMOS circuit because its power consumption is small.